ARGroup Aleš Ruda

ARBot hardware

by Administrator 14. October 2013 11:05

ARBot over the years has undergone several modifications. Its first version was prepared from the following components:

Of the component I constructed an experimental version of which was also reflected first problem. Smooth wheels work well on linu or wood flooring , but the ground slipping a robot is difficult to move.

 

ARBot - first attempt
ARBot - first attempt

Smooth wheels I mistook for outdoor version with 110 mm diameter. 

ARBot - first release after adjustments
ARBot - first release after adjustments

Another problem that could not be long to wait for the GPS. It turned out that the very serious problem with the signal reception near the Blackfin processor. For good, it was necessary to put GPS in a distance of about 50 cm from the DSP. This was not acceptable, so I chose LEA - 5H GPS from uBlox, which is substantially more interference. And if that was not enough so I found out by measuring the compass CMPS03 has a pretty bad transfer characteristics. Error 15 degrees is no problem. Graph unfortunately ended up somewhere in the dustbin of history and thus have no choice but to believe. Compass has been replaced by excellent AHRS module VN-100 from VectorNav. Which proved to be an excellent choice. Another modification was the replacement of motor units MD23, which solidified for better MD25. The last "blow" the decision of the organizers Robotur a duty to carry 5l keg of beer.

 

The final robot is composed of:

  • chassis A4WD1 from Lynxmotion,
  • 2 pcs MD25 motor controller,
  • 4 pcs EMG30 motors,
  • 4 pcs outdoor wheels 110 mm,
  • 3 pcs SRF08 sonar,
  • GPS uBlox LEA-5H,
  • AHRS vectornav VN-100,
  • OLED display μOLED-3202X-P1T
  • Control unit SRV01 with DSP BF537, camera OV9655 and WiFi module,
  • 10x NiMH 4,5 Ah.
ARBot - final version
ARBot - final version
ARBot - a look behind the scenes
ARBot - a look behind the scenes

Tags:

ARBot

ARBot wins Robotour in Lodz

by Administrator 23. September 2013 11:53
Cup

This year Robotour held in Poland Lodz, under the auspices of the local university. The robots chasing after conservation park Jozef Poniatowkiego. The weather was great so the only inconvenience was a tragic traffic situation. The last 150 km before Lodz we drove 3.5 hours.

Zero round - test run went very well until the goal, where robot instead turned back to the start began to circle around. Some kind of bug? Actually two. Robot does not circle. In turn should reduce the speed so that the right to prevent rolling. A second was to turn around and go to the start. The repair was time enough, so I started with her. The forward speed was due to the test in the past commented out and return to the start lacked one condition. I entered the target coordinates for first round and go to the start.

First round - starting whistle - minute countdown and ... nothing. Robot just flinches and stopped. At that moment I remembered the night before as I'm Martin said that the working of things not reach. I was pissed at myself. Well what 50 minutes would be enough to fix, you may just be a bug in one line with the requirement to return to the start. And exactly according to Murphy's law was. Do this test and go to the second round. But what!? Robot that moment lame the rear wheels, which stopped spinning. Similarly, I once solidified MD23 motor drive. The fact I've seen all the numerous! Time the second round came and it was not what solved. Be the it works or not.

Second round - robot is started, so I relieved. It is true that after a few tens of meters in rod began to bend oddly stuff right and then robot turned into strange paths, but after a few meters it turned and went back to the right path. After a few tens of meters again pulled to the right. He turned in the opposite direction and about 10 meters returned, followed by a turn in the right direction. Such an interesting eight. This is repeated once more, but fortunately still kept on the road. Gradually more and more robot beeps announcing the voltage drop on the battery cells. The final straights already passed unproblematic. Finished he turned and went the other way to start. After about 100 meters refers was whistled constantly and almost stopped moving. The battery was on the bottom. And so the robot stopped. Super performance.

3rd round - after a brief charging the robot started again. Managed properly turn twice and then stopped 150 meters from the target on uneven terrain when it got two wheels in the air. I was so in round best.

4th round - start from the first position. Initial lousy mood was gone. Robot perfectly drove home stretch and after the turn began to tour the bench unfortunately towards the lawn.


[youtube:Xxb1eJOH4Kc]

ARBot takes first place after counting results from all 4 rounds.

At this point I would like to thank all the organizers for the wonderful effort.
 

Thanks 

 

 

 

Tags:

ARBot

AXI stream VGA

by Administrator 11. May 2013 07:58

I need display data from stereoscopic camera. Use VGA is quick and easy solution. VGA timing is possible found on internet (for example here) or here is calculator.

Function is trivial. Process generates synchronization pulses and reads data from AXI stream. Reading ends when TUSER assert except the first pixel and reading begins on first pixel.

----------------------------------------------------------------------------------
-- Company: www.arbot.cz 
-- Engineer: ALes Ruda 
-- 
-- Create Date: 04/04/2013 07:41:10 PM
-- Module Name: AxiStreamVGA
-- Description:
-- From Axi video stream generates VGA color and timing signals. 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Library UNIMACRO;
use UNIMACRO.vcomponents.all;

entity AxiStreamVGA is
    Generic 
        (
        color_len: positive:=4;  -- number of color bits
        hor_s: positive:=120;    -- horizontal synchronization pulse width in pixel clock
        hor_bp: positive:=88;    -- horizontal back porch in pixel clock
        hor_d: positive:=752;    -- horizontal data length in pixel clock
        hor_fp: positive:=80;    -- horizontal front porch in pixel clock
        hor_pol: std_logic:='1'; -- horizontal synchronization pulse polarity (0- 111101111, 1-000010000)
        vert_s: positive:=6;     -- vertical synchronization pulse width (number of lines)
        vert_bp: positive:=83;   -- vertical back porch (number of lines)
        vert_d: positive:=480;   -- vertical data length (number of lines)
        vert_fp: positive:=97;   -- vertical front porch (number of lines)
        vert_pol: std_logic:='1' -- vertical synchronization pulse polarity (0- 111101111, 1-000010000)
        );
    Port 
        (
        ACLK		    : in 	std_logic;      -- AXI stream clock
        ARESETN		    : in	std_logic;      -- reset  
        S_AXIS_TVALID	: in	std_logic;      -- master generates data on S_AXIS_TDATA  
        S_AXIS_TDATA	: in	std_logic_vector(3*color_len-1 downto 0); -- data R & G & B
        S_AXIS_TLAST	: in	std_logic;      -- '1' marks last pixel on the line
        S_AXIS_TREADY	: out	std_logic;      -- AXI stream VGA is ready to recieve data
        S_AXIS_TUSER	: in	std_logic;      -- '1' marks first pixel on the frame - start of frame
 
        err             : out	std_logic;      -- '1' indicates error - fifo full
 
        PIXELCLK        : in	std_logic;      -- pixel clock
        VGA_HS      	: out	std_logic;      -- horizontal synchronization pulse 
        VGA_VS	        : out	std_logic;      -- vertical synchronization pulse
        VGA_R	        : out	std_logic_vector(color_len-1 downto 0);  -- RED color
        VGA_G	        : out	std_logic_vector(color_len-1 downto 0);  -- GREEN color
        VGA_B	        : out	std_logic_vector(color_len-1 downto 0)   -- BLUE color
        );
end AxiStreamVGA;

architecture Behavioral of AxiStreamVGA is

type state is (sync, back_porch, data, front_porch);
subtype AxiStreamVGACntType is integer range 0 to 4095;

signal hor_state	  : state;
signal vert_state	  : state;
signal hor_cnt        : AxiStreamVGACntType;
signal vert_cnt       : AxiStreamVGACntType;

signal loc_data    : std_logic_vector(3*color_len+1 downto 0);
signal loc_dataout : std_logic_vector(3*color_len+1 downto 0);
signal loc_tuser   : std_logic;


signal loc_ffrden  : std_logic;
signal loc_ffwren  : std_logic;
signal loc_fffull  : std_logic;
signal loc_ffrdcount    : std_logic_vector(9 downto 0);
signal loc_ffwrcount    : std_logic_vector(9 downto 0);

signal aRst        : std_logic;

begin

arst<=not ARESETN;
loc_data<=S_AXIS_TLAST & S_AXIS_TUSER & S_AXIS_TDATA; 
loc_tuser<=loc_dataout(3*color_len);
S_AXIS_TREADY<=not loc_fffull and ARESETN;
loc_ffwren<=not loc_fffull and S_AXIS_TVALID and ARESETN;  
loc_ffrden<= ARESETN when hor_state=data and vert_state=data and (loc_tuser='0' or (hor_cnt=hor_d-1 and vert_cnt=vert_d-1)) else '0';  


FIFO_inst : FIFO_DUALCLOCK_MACRO
   generic map (
      DEVICE => "7SERIES",            -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES" 
      ALMOST_FULL_OFFSET => X"0080",  -- Sets almost full threshold
      ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
      DATA_WIDTH => 3*color_len+2,   -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
      FIFO_SIZE => "18Kb",            -- Target BRAM, "18Kb" or "36Kb" 
      FIRST_WORD_FALL_THROUGH => true) -- Sets the FIFO FWFT to TRUE or FALSE
   port map (
      ALMOSTEMPTY => open,          -- 1-bit output almost empty
      ALMOSTFULL => open,           -- 1-bit output almost full
      DO => loc_dataout,            -- Output data, width defined by DATA_WIDTH parameter
      EMPTY => open,                -- 1-bit output empty
      FULL => loc_fffull,           -- 1-bit output full
      RDCOUNT => loc_ffrdcount,     -- Output read count, width determined by FIFO depth
      RDERR => err,                 -- 1-bit output read error
      WRCOUNT => loc_ffwrcount,     -- Output write count, width determined by FIFO depth
      WRERR => open,                -- 1-bit output write error
      DI => loc_data,               -- Input data, width defined by DATA_WIDTH parameter
      RDCLK => PIXELCLK,            -- 1-bit input read clock
      RDEN => loc_ffrden,           -- 1-bit input read enable
      RST => aRst,                  -- 1-bit input reset
      WRCLK => ACLK,                -- 1-bit input write clock
      WREN => loc_ffwren            -- 1-bit input write enable
   );


process (PIXELCLK, loc_tuser)
    variable r: std_logic_vector(color_len-1 downto 0);
    variable g: std_logic_vector(color_len-1 downto 0);
    variable b: std_logic_vector(color_len-1 downto 0);
    
begin
 
 if PIXELCLK'event and PIXELCLK='1' then
   case hor_state is
     when sync =>
       VGA_HS<=hor_pol;
	   if hor_cnt=0 then
    	 hor_cnt<=hor_bp-1;
         hor_state<=back_porch;
       else
         hor_cnt<=hor_cnt-1;
       end if;                		          
     when back_porch =>
       VGA_HS<=not hor_pol;
       if hor_cnt=0 then
    	 hor_cnt<=hor_d-1;
         hor_state<=data;
       else
         hor_cnt<=hor_cnt-1;
       end if;                		          
     when data =>
       if vert_state=data then
         r:=loc_dataout(3*color_len-1 downto 2*color_len);  
         g:=loc_dataout(2*color_len-1 downto color_len);  
         b:=loc_dataout(color_len-1 downto 0);  
	   else	
         r:=(others=>'0');  
         g:=(others=>'0');  
         b:=(others=>'0');  
       end if;                		          
       if hor_cnt=0 then
         hor_cnt<=hor_fp-1;
         hor_state<=front_porch;
       else
         hor_cnt<=hor_cnt-1;
       end if;                		          
     when front_porch =>
       r:=(others=>'0');  
       g:=(others=>'0');  
       b:=(others=>'0');  
       if hor_cnt=0 then
         hor_cnt<=hor_s-1;
         hor_state<=sync;

         case vert_state is
           when sync =>
             VGA_VS<=vert_pol;
	         if vert_cnt=0 then
    	       vert_cnt<=vert_bp;
               vert_state<=back_porch;
             else
               vert_cnt<=vert_cnt-1;
             end if;                		          
           when back_porch =>
             VGA_VS<=not vert_pol;
   	         if vert_cnt=0 then
               vert_cnt<=vert_d-1;
               vert_state<=data;
             else
               vert_cnt<=vert_cnt-1;
             end if;                		          
           when data =>
             if vert_cnt=0 then
               vert_cnt<=vert_fp-1;
               vert_state<=front_porch;
             else
               vert_cnt<=vert_cnt-1;
             end if;                		          
           when front_porch =>
             if vert_cnt=0 then
               vert_cnt<=vert_s-1;
               vert_state<=sync;
             else
               vert_cnt<=vert_cnt-1;
             end if;                		          
         end case;
       else
         hor_cnt<=hor_cnt-1;
       end if;                		          
   end case;
   if ARESETN='0' then
       hor_state<=sync;			
       hor_cnt<=hor_s-1;
       vert_state<=sync;
       vert_cnt<=vert_s-1;
       VGA_VS<=not vert_pol;
       VGA_HS<=not hor_pol;
       r:=(others=>'0');  
       g:=(others=>'0');  
       b:=(others=>'0');  
   end if;
 end if;
 
 VGA_R<=r;     
 VGA_G<=g;     
 VGA_B<=b;     
end process;


end Behavioral;

AxiStreamVGA.rar (2,16 kb)

Tags:

ZedBoard

AXI VDMA on ZedBoard

by Administrator 20. March 2013 09:07

I use AXI VDMA IP for store data from stereoscopic camera to the memory. I search example how to use xilinx_dma.c driver. I found information about xvdma.c driver who works as bridge between base VDMA kernel driver and user application, but I am not able to compile it.

Here is my simple solution. I use mmap to access VDMA IP registers and program it. Frame buffers is allocated on end of DDR memory. To prevent use this memory by kernel add mem option to bootargs in devicetree.dts.

  1. Changes in devicetree.dts
    bootargs = "consoleblank=0 root=/dev/mmcblk0p2 rw rootwait earlyprintk mem=224M";
    
  2. main.c
    #include 
    #include 
    #include 
    #include 
    
    #include "VDMA.h"
    
    #define VDMAWidth 752
    #define VDMAHeight 480
    #define VDMAPixelWidth 8
    #define VDMAFB1Adr 0x1e000000
    #define VDMAFB2Adr 0x1f000000
    #define VDMABaseAddr 0x43000000
    
    
    int main()
    {
    	VDMA_info vdma;
    
    	VDMA_Init(&vdma, VDMABaseAddr, VDMAWidth, VDMAHeight, VDMAPixelWidth, VDMAFB1Adr, VDMAFB2Adr);
    
    	VDMA_Start(&vdma, VDMAFB1Adr);
    
    	printf("Waiting for end...\n");
    	while(VDMA_IsDone(&vdma)==0);
    
    	VDMA_UnInit(&vdma);
    }
    
    
  3. VDMA.c
    /*
     * VDMA.h
     *
     *  Created on: 16.3.2013
     *      Author: Ales
     */
    
    #ifndef VDMA_H_
    #define VDMA_H_
    
    #include
    
    #define VDMACount 64
    #define VDMAMapLen VDMACount*4
    
    typedef struct
    {
        unsigned int baseAddr;
        int vdmaHandler;
        int width;
        int height;
        int pixelLength;
        int fbLength;
        unsigned int* vdmaVirtualAddress;
        unsigned int* fb1VirtualAddress;
        unsigned int* fb2VirtualAddress;
    
        pthread_mutex_t lock;
    } VDMA_info;
    
    int VDMA_Init(VDMA_info *info, unsigned int baseAddr, int width, int height, int pixelLength, unsigned int fb1Addr, unsigned int fb2Addr);
    void VDMA_UnInit(VDMA_info *info);
    unsigned int VDMA_Get(VDMA_info *info, int num);
    void VDMA_Set(VDMA_info *info, int num, unsigned int val);
    void VDMA_Start(VDMA_info *info, unsigned int adr);
    void VDMA_OutStart(VDMA_info *info, unsigned int adr, int circular);
    int VDMA_IsRunning(VDMA_info *info);
    int VDMA_IsDone(VDMA_info *info);
    void VDMA_Disp(VDMA_info *info, char *str, int num);
    
    
    #endif /* VDMA_H_ */
    
    
  4. VDMA.c
    /*
     * VDMA.c
     *
     *  Created on: 17.3.2013
     *      Author: Ales Ruda
     *      web: www.arbot.cz
     */
    
    #include "VDMA.h"
    #include 
    #include 
    #include 
    #include <sys/mman.h>
    
    int VDMA_Init(VDMA_info *info, unsigned int baseAddr, int width, int height, int pixelLength, unsigned int fb1Addr, unsigned int fb2Addr)
    {
    	info->baseAddr=baseAddr;
    	info->width=width;
    	info->height=height;
    	info->pixelLength=pixelLength;
    	info->fbLength=pixelLength*width*height;
        info->vdmaHandler = open("/dev/mem", O_RDWR);
        info->vdmaVirtualAddress = (unsigned int*)mmap(NULL, VDMAMapLen, PROT_READ | PROT_WRITE, MAP_SHARED, info->vdmaHandler, (off_t)info->baseAddr);
        if(info->vdmaVirtualAddress == MAP_FAILED)
        {
         perror("vdmaVirtualAddress mapping for absolute memory access failed.\n");
         return -1;
        }
        info->fb1VirtualAddress = (unsigned int*)mmap(NULL, info->fbLength, PROT_READ | PROT_WRITE, MAP_SHARED, info->vdmaHandler, (off_t)fb1Addr);
        if(info->fb1VirtualAddress == MAP_FAILED)
        {
         perror("fb1VirtualAddress mapping for absolute memory access failed.\n");
         return -2;
        }
        info->fb2VirtualAddress = (unsigned int*)mmap(NULL, info->fbLength, PROT_READ | PROT_WRITE, MAP_SHARED, info->vdmaHandler, (off_t)fb2Addr);
        if(info->fb2VirtualAddress == MAP_FAILED)
        {
         perror("fb2VirtualAddress mapping for absolute memory access failed.\n");
         return -3;
        }
    
        return 0;
    }
    
    void VDMA_UnInit(VDMA_info *info)
    {
        munmap((void *)info->vdmaVirtualAddress, VDMAMapLen);
        munmap((void *)info->fb1VirtualAddress, info->fbLength);
        munmap((void *)info->fb2VirtualAddress, info->fbLength);
        close(info->vdmaHandler);
    }
    
    unsigned int VDMA_Get(VDMA_info *info, int num)
    {
    	if(num>=0 && num<VDMACount)
    	{
    		return info->vdmaVirtualAddress[num];
    	}
    	return 0;
    }
    
    void VDMA_Set(VDMA_info *info, int num, unsigned int val)
    {
    	if(num>=0 && num<VDMACount)
    	{
    		info->vdmaVirtualAddress[num]=val;
    	}
    }
    
    void VDMA_OutStart(VDMA_info *info, unsigned int adr, int circular)
    {
    	VDMA_Disp(info, "status ", 0x04/4);
    	VDMA_Disp(info, "control ", 0x00/4);
    
    	VDMA_Set(info, 0x00/4, circular==1?4+2:4);  // MM2S_DMACR: reset
    
    	while((VDMA_Get(info, 0x00/4)&4)==4); // wait for reset end
    
    	VDMA_Disp(info, "status ", 0x04/4);
    	VDMA_Set(info, 0x04/4, 0xffffffff);  // S2MM_DMASR: remove errors
    	VDMA_Disp(info, "status ", 0004/4);
    
    	usleep(100000);
    
    	VDMA_Set(info, 0x18/4, 1);  // MM2S_FRMSTORE: 1
    
    	VDMA_Set(info, 0x00/4, circular==1?2+1:1);  // S2MM_DMACR: RS
    	// wait for run
    	while((VDMA_Get(info, 0x00/4)&1)==0 || (VDMA_Get(info, 0x04/4)&1)==1)
    	{
    		VDMA_Disp(info, "status ", 0004/4);
    		VDMA_Disp(info, "control ", 0x00/4);
    	}
    
    	VDMA_Set(info, 0x28/4, 0); // this alters s2mm park ptr
    
    	VDMA_Set(info, 0x5C/4, adr); //adr1
    //	VDMA_Set(info, 0x60/4, adr); //adr2
    
    	VDMA_Set(info, 0x58/4, info->pixelLength*info->width);  // stride length in bytes
    
    	VDMA_Set(info, 0x54/4, info->pixelLength*info->width);  // length in bytes
    
        VDMA_Set(info, 0x50/4, info->height);  // height and start
    
        VDMA_Disp(info, "status ", 0x04/4);
    	VDMA_Disp(info, "control ", 0x00/4);
    	VDMA_Disp(info, "Park", 0x28/4);
    }
    
    void VDMA_Start(VDMA_info *info, unsigned int adr)
    {
    	VDMA_Set(info, 0x30/4, 64+4);  // S2MM_DMACR: sof=tuser, reset
    
    	while((VDMA_Get(info, 0x30/4)&4)==4); // wait for reset end
    
    	VDMA_Disp(info, "status ", 0x34/4);
    	VDMA_Set(info, 0x34/4, 0xffffffff);  // S2MM_DMASR: remove errors
    	VDMA_Disp(info, "status ", 0x34/4);
    
    
    	VDMA_Set(info, 0x30/4, 64+1);  // S2MM_DMACR: sof=tuser, RS
    // wait for run
    	while((VDMA_Get(info, 0x30/4)&1)==0 || (VDMA_Get(info, 0x34/4)&1)==1)
    	{
    		VDMA_Disp(info, "status ", 0x34/4);
    		VDMA_Disp(info, "control ", 0x30/4);
    	}
    
    	VDMA_Set(info, 0xAC/4, adr);
    	VDMA_Set(info, 0x28/4, 0);
    
    	VDMA_Set(info, 0xA8/4, info->pixelLength*info->width);  // stride length in bytes
    
    	VDMA_Set(info, 0xA4/4, info->pixelLength*info->width);  // length in bytes
    
        VDMA_Set(info, 0xA0/4, info->height);  // height and start
    	VDMA_Disp(info, "status ", 0x34/4);
    	VDMA_Disp(info, "control ", 0x30/4);
    }
    
    int VDMA_IsRunning(VDMA_info *info)
    {
    	return (VDMA_Get(info, 0x34/4)&1)==1;
    }
    
    int VDMA_IsDone(VDMA_info *info)
    {
    	return (VDMA_Get(info, 0x34/4)&0x01000)!=0;
    }
    
    void VDMA_Disp(VDMA_info *info, char *str, int num)
    {
    	printf("%s(%02x)=%08x\n", str, num, VDMA_Get(info, num));
    }
    
    

Source files vdma.rar (2,01 kb)

Tags:

ZedBoard

How to get working PS I2C in Xillinux

by Administrator 14. November 2012 12:31

I would like to join camera Aptina MT9V034 to the ZedBoard. The camera is configured via I2C bus and video data will be processed using the PL. To save PL resources I want to use PS I2C.

  1. Configure I2C in XPS. Double click on system.xmp in the "boot image creation kit"\system. In my case MIO 10..11.
    Zynq configuration
    Zynq configuration
  2. It is necessary to rebuild FSBL. From XPS export a project to the SDK and add new standalone project Zynq FSBL. Select Release configuration and rebuildit project. Copy compiled ... \Release\FSBL.elf to "boot image creation kit"\boot.
  3. Regenerate boot.bin. Run the makeboot.bat In the folder "boot image creation kit"\boot and resulting boot.bit copy to first partition of the SD card.
  4. Recompile the kernel.
    1. Download sources.
      $ git clone https://github.com/Digilent/linux-3.3-digilent.git
    2. Apply patches from "/usr/src/xillinux/kernel-patches".
    3. Edit ".config". Set CONFIG_I2C_CHARDEV option to y.
    4. $ make
    5. Copy arch/arm/boot/zImage to the first partition of the SD card.
  5. Edit DTS.
    1. Decompile a DTB.
      $ dtc -I dtb -O dts -o devicetree.dts devicetree.dtb
    2. To node ax@0 in devicetree.dts supplement.
      i2c0: i2c @ e0004000 
        {
         compatible = "xlnx, PS7-i2c-1.00.a";
         reg = <0x1000 0xE0004000>;
         interrupts = <0 25 0>;
         interrupt-parent = <1>;
         bus-id = <0>;
         input-clk = <111111111>;
         i2c-clk = <100000>;
         # address-cells = <1>;
         # size-cells = <0>;
        };
      
    3. Compile DTB.
      $ dtc -I dts -O dtb -o devicetree.dtb devicetree.dts
  6. Reboot ZedBoard.
  7. In /dev exists i2c-0.
  8. Type
    $ I2cdetect-l
    i2c-0 i2c XILINX I2C I2C adapter at e0004000
I2C
I2C

Tags:

ZedBoard

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